Implement the scheme below in verilog and carry out simulations to check the functionalities

Description of the scheme $+$ special requirements:

The circuit above is a circuit that processes text $($letters received in asci code, only lowercase letters$)$ and performs

$2$ functions:

separates vowels from consonants and saves them separately in $2$ ram memories.

check if the password has been entered $($successive sequence of letters$)$ and activate the "check" signal if yes.

counter$\_6$b $-$ counter.

reg$\_6$b $-$ register used to delay the address change by one clock cycle.

demux $-$ demultiplexer.

ram$\_$consonants $+$ ram$\_$vowels $-$ ram memory module with $64$ locations of $8b$ each. Asynchronous reading.

vowel$\_$checker$\_$struct $-$ combinational circuit that checks whether the entered letter is a vowel or not. Written using

a structural description to highlight the hardware structures used.

pass$\_$check$\_$fsm $-$ automatically checks if the password has been entered. Activates "pass$\_$ok$"$ for $1$ single clock

cycle in case of correct input. The password consists of the first $5$ letters of your first and last name concatenated

$($eg: for ion vasilescu: pass$=$ionva, madalin vasilescu: pass$=$madal$).$ A letter is considered only if the $"$en$"$ signal is

also activated.

Add the dimensions corresponding to the threads, where you think you should. These were not put on the drawing.

To simplify the drawing, the clock and reset wire was not actually drawn. Don't forget to put it on$.$

For simulation:

For functionality testing, the circuit will be allowed to operate for $500$ clock cycles.

$2$ data sequences will be generated and saved in the RAM memory:

abcdef

the correct password so that pass$\_$check$\_$fsm is tested..