In a cache system we have the following attributes: $256MB$ of physical memory space

$4MB$ of cache $256KB$ per cache line

a$)$ Determine number of lines in cache.

b$)$ Determine the number of address bits out of the processor.

c$)$ Determine the number of bits needed for the block offset section of the address.

d$)$ If our cache is $4-$way set associative, how many sets are there in the cache?

c$)$ How many bits are needed to select sets in this cache?

f$)$ Determine the number of bits of the tag, if $8-$way set associative eache is implemented.

g$)$ Fill the table below with proper number of bits in each portion of the address bit map: