In a VHDL$-$based keypad scanner, what technique is used to reduce the number of input$/$output pins needed? Ops: A$.$ Multiplexing each key B$.$ Using a matrix keypad arrangement C$.$ Employing a serial$-$to$-$parallel converter D$.$ Using a decoder for each keyWhat power optimization technique can be applied to VHDL state machines to reduce dynamic power consumption? Ops: A$.$ Using high$-$frequency clocks B$.$ Implementing clock gating C$.$ Increasing the number of states D$.$ O Utilizing larger transistorsWhich of the following describes the structure of VHDL code correctly? Ops: A$.$ Library Declaration; Entity Declaration; Architecture Declaration; Configurations B$.$ Entity Declaration; Configuration; Library Declaration; Architecture Declaration C$.$ Configuration; Library Declaration; Entity Declaration; Architecture Declaration D$.$ O Library Declaration; Configuration; Entity Declaration; Architecture DeclarationIn general, an n$-$bit$-$by$-$n$-$bit array multiplier would require half$-$adders. Ops: A$.$ On$,$ n$($n$-2),$ n$2$ B$.$ On$($n$-2),$ n$,$ n$2$ C$.$ On$2,$ n $($n$-2),$ n D$.$ None of these