In class we covered the $$LLPex$$ example, and did constraint graphs for the normal code, and for

a version that was $2$x unrolled $($i$.$e$.$ the loop body handles both $[$X$0,$ #$0]$ and $[$X$0,$ #$1]$ and

compiler register renamed. For this homework, do the following. NOTE: We are ONLY

scheduling the body of the loop $$ you can ignore the ADDI at the beginning to initialize the loop

variable. Also, when scheduling do NOT change the code, just schedule what you produced in

the previous steps, or got from lecture:

a$.)$ Create a $4$x unrolled version of the code $($let$$s call it LLPex$4)$ with compiler register

renaming $($i$.$e$.$ use different registers in the code to increase parallelism, but do NOT

assume hardware register renaming, the a$0\mathrm{.}1$ stuff$).$

b$.)$ Draw the constraint graph for LLPex$4.$ Each edge of the constraint graph should indicate

the cause $($i$.$e$.$RAW X$0,$Control$,$ etc.$).$

c$.)$ Schedule both LLPex $($the original code$)$ and LLPex$4$ onto the lab #$4$ processor.

d$.)$ Schedule both LLPex and LLPex$4$ onto a $2-$way VLIW. Both issue slots can do ALU

operations, and both can do branch operations. Only one of the issue slots is allowed to

do loads and stores. There are load delay slots $($cannot use the value loaded in the

subsequent cycle$),$ and branch delay slots $($the other instruction in the same cycle, and

both instructions in the next cycle, ALWAYS execute regardless of whether the branch is

taken or not$).$

For #$3$ and #$4$ please make sure the code schedule is as short as possible.