In estimating the performance of the single-cycle implementation, assume that only the major functional units have delays (assume the delay of multiplexers, control unit. PC access, etc. are negligible) The operational timing for each of the major functional units are: Memory units: 300 ps ALU and Adders: 100 ps Register file (read or write): 200 ps Where ps stands for picoseconds (I ps-1x 10-12 seconds) For the single cycle implementation and for each of the 5 instruction classes, identify critical paths in the implementation and determine the time taken to complete each instruction