In the following code, all signals are $1-$bit std$\_$logic. Draw a logic diagram that corresponds to the code. Assume

that a D ip$-$ op with CE is available.

F $<=$ A when EA $=\text{'}1\text{'}$ else B when EB $=\text{'}1\text{'}$ else $\text{'}$Z$\text{'}$;

process$($CLK$)$

begin

if CLK'event and CLK $=\text{'}1\text{'}$ then

if Ld $=\text{'}1\text{'}$ then A $<=$ B; end if;

if Cm $=\text{'}1\text{'}$ then A $<=$ not A; end if;

end if;

end process;