In the following doubly-nested loop, suppose none of the array elements are allocated to registers, but all scalar variables are in registers.

Suppose the cache is 4-way set-associative, with the FIFO replacement policy and the block size of one word. The total cache size (for data) to is 8K words. What is the highest possible cache miss ratio when the processor executes the following doubly-nested loop? What is the highest possible cache hit ratio when the processor executes the following loop? You must clearly explain how you derive your answer, taking into account of possibilities of data layout in practice. (We assume that initially the cache is cold.)

for (i=1; i

D[i] = (A[i]+B[i])/C[i];

A[i]= (E[i]-D[i])/3.0;

}

}