In the following processor design, when executing the instruction beg $$s1,$$$t1,$ offset, please answer:

what would be the output of the logic block highlighted in red $(4$ points$)$

what would be the next PC value? $(8$ points$)$

what type of addressing method is used? $(4$ points$)$

We assume that before the instruction is executed, both $$t1$ and $$s1$ store a value of $0,$ the offset is $10($in decimal$),$ and the current PC value is $80012.$

$($hint$.$ reviow lerture $6$ and lerture $19)$