In the following question, TYPE-1 and TYPE-2 represent the type of the FSM as follows: TYPE-1: Mealy TYPE-2: Moore In this question we will design a sequential circuit where you have a 1-bit input X and a l-bit output Y. Y should be 1 if and only if the values of X have been either 0-0-0 or 1-1-1 on the three most recent rising edges of CLK. Assume you have a resettable D FF and when there is a reset you start with initial state SO. a) Derive the state diagram for a TYPE-1 system by completing the below diagram. b) Design the same circuit using a shift register approach, where you should use a TYPE-2 output logic reset SO In the following question, TYPE-1 and TYPE-2 represent the type of the FSM as follows: TYPE-1: Mealy TYPE-2: Moore In this question we will design a sequential circuit where you have a 1-bit input X and a 1-bit output Y. Y should be lif and only if the values of X have been either 0-0-0 or 1-1-1 on the three most recent rising edges of CLK. Assume you have a resettable D FF and when there is a reset you start with initial state SO. a) Derive the state diagram for a TYPE-1 system by completing the below diagram. b) Design the same circuit using a shift register approach, where you should use a TYPE-2 output logic reset SO