In the following SystemVerilog code, if a $=4\text{'}$b$1100$ and b $=4\text{'}$b$0101,$ what will be the value of sum and

overflow?

module add$($input logic $[3$:$0]$ a$,$ b$,$ output logic $[3$:$0]$ sum, output logic

overflow$)$;

assign $\{$overflow$,$ sum$\}=$ a $+$ b;

endmodule

A$.$ sum $=4\text{'}$b$1001,$ overflow $=1$

B$.$ sum $=4\text{'}$b$0001,$ overflow $=1$

C$.$ sum $=4\text{'}$b$0001,$ overflow $=0$

D$.$ sum $=4\text{'}$b$0001,$ overflow $=1$

E$.$ sum $=4\text{'}$b$0001,$ overflow $=0$