Question: In the pre-lab, you will use Quartus to build a full adder. Recall that the full adder takes inputs A, B, and Cin, and produces

In the pre-lab, you will use Quartus to build a full adder. Recall that the full adder takes inputs A, B, and Cin, and produces outputs S and Cout. Design and compile a full adder circuit in SystemVerilog. Save the file as fulladd.sv. Simulate fulladd.sv using Questa. Verify all test cases. In lab, you will build a 4-bit adder. To prepare for the simulation, determine at least four test cases for your simulation. These cases should verify that adding two unsigned numbers give the correct outputs in all situations. In other words, you want to be sure that the carry-out is 0 or 1 when expected. For each test case, explain what it is supposed to test and why you are including it.

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