In the SystemVerilog implementation of the cache controller described, what is the primary purpose of the cache$\_$tag$\_$type structure?

Group of answer choices

To define the interface between the cache controller and the CPU, including address and data fields.

To implement the memory request and response protocols between the cache and memory.

To describe the attributes of a cache line, including the valid bit, dirty bit, and tag field.

To manage the state transitions of the finite$-$state machine $($FSM$)$ used to control the cache.