In this assignment we will be modifying the capacity of a cache which can replace the instruction ram ian our CPU design.

Description

Download this Download thissolution package. Open the read$\_$cache.circ from the package. It contains three circuits:

$1)$ A top$-$level Main circuit, which provides circuity that feeds a sequence of memory addresses to the cache.

$2)$ An AssocCache circuit, which implements a $2-$way $16-$bit $16-$block associative cache, with LRU replacement policy.

$3)$ A Memory circuit, which models the main memory where $512$ bytes $(256$x $16-$bit data$)$ is stored. Misses from the associative cache are retrieved from here and stored to the cache.

Load the Address Sequence ram in the Main circuit with the Assoc$\_$AddrsSeq.txt image. Load the Main Memory ram in the Memory circuit with the Assoc$\_$memData.txt image $($be careful here to load the correct instance of the Memory ram with the image; do so by double clicking on the embedded instance of the circuits, not the one in side panel$).$ Run the clock until Done led in the Main circuit goes high. Verify that you achieve a hit rate of $6/64.$

Familiarize yourself with the circuit. Notice how we are assigning bits to Tag, Data, Valid and Age for each entry in the cache.

Objective $1$

Increase the capacity of the Associative Cache by $4$x$.$ There are multiple ways of doing this. What is the resultant hit rate? Add the circuit to your assignment solution.

Objective $2$

Modify the Address Sequence to generate an exact $12/64$ hit rate on the final circuit. There are lots of ways of doing this. Save your modified Address Sequence ram content and add to your assignment solution.

Zip the two files and submit it as the solution.