In this exercise, we assume that the following MIPS code is executed on a pipelined processor with a 5-stage pipeline (IF, ID, EX, MEM, WB), full forwarding, and a predict-taken branch predictor. Hints: First find data dependencies. Then examine if these dependencies can cause data hazard. Branch instruction can cause control hazards. Instructions will be flushed if the prediction is wrong. LW R2, 0 (R1) BEQ R2, RO, LABEL2 LW R3, 0 (R2) BEQ R3, RO, LABEL1 ADD R1, R3 LABEL1: #Not taken once, then always taken #Always taken , R1 SW R1, 0 (R2) ADD R4, R5, R6 LABEL2: Draw the pipeline execution diagram for this code, assuming that branches execute in the EX stage. 1 3. 7 8. 9 10 11 12 13 14 15 LW R2, 0 (R1) IF ID EX MEMWB BEQ R2, RO, LABEL2 IF