In this exercise we compare the performance of 1-issue and 2-issue processors, taking into account program transformations that can be made to optimize for 2-issue execution. Problems in this exercise refer to the following loop (written in C): 3. Translate this C code into MIPS instructions. Your translation should be direct, without rearranging instructions to achieve better performance. When writing MIPS code, assume that variables are kept in registers as follows, and that all registers except those indicated as Free are used to keep various variables, so they cannot be used for anything else. a. Free R5 R6 R1 R2 R3 R10, R11, R12 b. If the loop exits after executing only two iterations, draw a pipeline diagram for your MIPS code from Part a executed on a 2-issue processor. Assume the processor has perfect branch prediction and can fetch any two instructions (not just consecutive instructions) in the same cycle. Rearrange your code from Part a to achieve better performance on a 2-issue statically scheduled processor. Repeat Part b, but this time use your MIPS code from Part c. What is the speedup of going from a 1-issue processor to a 2-issue processor? Use your code from Part a for both 1-issue and 2-issue, and assume that 1,000,000 iterations of the loop are executed. As in Part b, assume that the processor has perfect branch predictions, and that a 2-issue processor can fetch any two instructions in the same cycle. c. d. e. In this exercise we compare the performance of 1-issue and 2-issue processors, taking into account program transformations that can be made to optimize for 2-issue execution. Problems in this exercise refer to the following loop (written in C): 3. Translate this C code into MIPS instructions. Your translation should be direct, without rearranging instructions to achieve better performance. When writing MIPS code, assume that variables are kept in registers as follows, and that all registers except those indicated as Free are used to keep various variables, so they cannot be used for anything else. a. Free R5 R6 R1 R2 R3 R10, R11, R12 b. If the loop exits after executing only two iterations, draw a pipeline diagram for your MIPS code from Part a executed on a 2-issue processor. Assume the processor has perfect branch prediction and can fetch any two instructions (not just consecutive instructions) in the same cycle. Rearrange your code from Part a to achieve better performance on a 2-issue statically scheduled processor. Repeat Part b, but this time use your MIPS code from Part c. What is the speedup of going from a 1-issue processor to a 2-issue processor? Use your code from Part a for both 1-issue and 2-issue, and assume that 1,000,000 iterations of the loop are executed. As in Part b, assume that the processor has perfect branch predictions, and that a 2-issue processor can fetch any two instructions in the same cycle. c. d. e