In this exercise, we examine how data dependences affect execution in the basic 5-stage pipeline described in Section 4.5. Problems in this exercise refer to the following sequence of instructions: ADD R1, R2, R3 SUB R2, R1, R2 XOR R1, R1, R2 Also, assume the following cycle times for each of the options related to forwarding. Without forwarding, there is no additional forwarding paths. Full forwarding means the pipeline has two forwarding paths: from EX/MEM to EX (also called ALU-ALU forwarding), and from MEM/WB to EX. Indicate dependences and their type (RAW, WAR, WAW, RAR). Assume that there is no forwarding in this pipelined processor. Please add nop instructions to ensure correctness. Assume that there is full forwarding. Please add nop instructions to ensure correctness. What is the total execution time (in wall clock time) of this instruction sequence without forwarding and with full forwarding? What is the speedup achieved by adding full forwarding to a pipeline that had no forwarding