In this exercise, well examine quantitatively the pros and cons of adding an addressing mode to RISC-V that allows arithmetic instructions to directly access memory, as found on the 80x86. The primary benefit is that fewer instructions will be executed because we wont have to first load a register. The primary disadvantage is that the cycle time will have to increase to account for the additional time to read memory. Consider adding a new instruction

addm $t2, 100($t3) $t2 = $t2 + Memory[$t3 + 100]

Assume that the new instruction will cause the cycle time to increase by 10%. Use the instruction frequencies for gcc benchmark from the following table:

Instruction Average CPI Frequency

gcc spice

Arithmetic 1.0 48% 50%

Data transfer 1.4 33% 41%

Conditional branch 1.7 17% 8%

Jump 1.2 2% 1%

Assume that two thirds of the data transfer instructions are loads and the rest are stores. Assume that the new instructions affect only the clock speed and not the CPI. What percentage of loads must be eliminated for the machine with the new instruction to have at least the same performance?