In this experiment, data buses and basic memory are going to be implemented by using three-state buffers. You can use any operator/code block in this experiment. Using multiplexer structure is forbidden. You must simulate the all parts and modules.

In this part, you should implement a 128 byte memory module using 32 byte memory module. 128 byte memory module should take 32-bit data as input and give 32-bit data as output. Also, this module should take address, reset, read enable, write enable and clock inputs. Your module should be able to perform the operations below. At the rising edge of the clock signal, the selected memory line should store the data value, which is given as input, if the write enable is high. . The module should clear the all stored data in the memory modules at the falling edge of the reset signal. If read enable is high, the output of the module should be the stored data of the selected memory line. Hint: 32 byte memory modules have 8-bit inputs and 8-bit outputs. You can use concatenate operation to implement 128 byte memory. In this part, you should implement a 128 byte memory module using 32 byte memory module. 128 byte memory module should take 32-bit data as input and give 32-bit data as output. Also, this module should take address, reset, read enable, write enable and clock inputs. Your module should be able to perform the operations below. At the rising edge of the clock signal, the selected memory line should store the data value, which is given as input, if the write enable is high. . The module should clear the all stored data in the memory modules at the falling edge of the reset signal. If read enable is high, the output of the module should be the stored data of the selected memory line. Hint: 32 byte memory modules have 8-bit inputs and 8-bit outputs. You can use concatenate operation to implement 128 byte memory