In this lab, you will design a serial receiver system that has the functionality of receiving a 4-bit data word in serial (1.e., one bit at a time) and converting it to a parallel format. While doing this, the system will also determine the parity of the received 4-bit word. The system accepts one input signal, RxD, in addition to the clock and presents three output signals - W, W OUT and P. Input RxD is the serial data input where data arrives one bit at a time, with each bit sampled on the rising edge of the clock provided to the system. After the 4-bit word is fully shifted in control signal output W_OUT is set high for one clock cycle while the data is made available at the 4-bit output W=[W; W2W, W.), where W; is the most significant bit. While the data W is available, output signal P is asserted (1. e., set high) if the parity of the received 4-bit word is odd otherwise Pis low. More details of the system are as follows. In this lab, you will design a serial receiver system that has the functionality of receiving a 4-bit data word in serial (1.e., one bit at a time) and converting it to a parallel format. While doing this, the system will also determine the parity of the received 4-bit word. The system accepts one input signal, RxD, in addition to the clock and presents three output signals - W, W OUT and P. Input RxD is the serial data input where data arrives one bit at a time, with each bit sampled on the rising edge of the clock provided to the system. After the 4-bit word is fully shifted in control signal output W_OUT is set high for one clock cycle while the data is made available at the 4-bit output W=[W; W2W, W.), where W; is the most significant bit. While the data W is available, output signal P is asserted (1. e., set high) if the parity of the received 4-bit word is odd otherwise Pis low. More details of the system are as follows