$.$ In this problem we compare CISC and RISC coding. The following table, write the

minimum$-$length CISC and RISC codes for computing three arithmetic operations in

a sequence: C $=$ A $+$ B$,$ E $=$ D $.$ C$,$ and F $=$ C $$ E$.$ All input operands A$,$ B$,$ C$,$ and D

are initially fetched from the data cache. The intermediate results C and E need not

be stored in the memory. But the final result F must be stored in the memory. Only $5$

instruction types: load, store, add, subtract, and multiply are allowed in writing

the minimum code sequences. At most one memory reference is allowed in any

instruction.

CISC code RISC code

$($Register memory architecture$)($Load Store$)$

$($b$)$ Assume for the CISC processor, it takes $2$ cycles to add, subtract, load, or store;

and $6$ cycles to multiply. On the RISC processor, it takes only $1$ cycle to add, subtract,

load, or store; and $2$ cycles to multiply. With a $1$ GHz clock to drive both processors,

calculate the effective CPI and the expected MIPS rates of the two processors to

execute the above two code sequences.