In this problem, you will port code to a simple $3-$issue VLIW machine, and schedule it to improve

performance. Details about the $3-$issue VLIW machine with $3$ fully pipelined functional units:

$$ Integer ALU with $1$ cycle latency to next Integer$/$FP

$$ Integer ALU with $2$ cycle latency to next Branch

$$ Memory Unit with $3-$cycle latency

$$ Floating Point Unit with $3-$cycle latency $($it can complete one add or one multiply per

clock cycle$)$

$$ Branch completed with $1$ cycle delay slot $($branch solved in ID stage$)$

$$ No interlocks