In this project, we will study memory system performance using M5 simulator and 8 SPECCPU benchmarks. Sample instruction size is 10M for each simulation.

M5 simulator information is available on course website.

Requirement:

Setup three-level caches in your memory system. Use typical cache and memory simulation configuration (Info. can be found in papers published in ISCA, HPCA, or MICRO and sample configuration files in M5). Papers are available under folder /space/source/paper/ on kani. Explain your setup in project report.

Run 8 simulations on uni-processor system (one simulation for each benchmark) and collect Instruction per Cycle (IPC) and level 3 cache miss rate for each benchmark. Draw the following Excel figures to compare the differences and analyze the results.

Figure 1 and analysis: Instruction per Cycle (IPC) for 8 benchmarks in the following order: [gzip, vpr, gcc, mcf, crafty, parser, eon, perlbmk].

Figure 2 and analysis: Level 3 cache miss rate for 8 benchmarks in the following order: [gzip, vpr, gcc, mcf, crafty, parser, eon, perlbmk].

Run simulations on 4-core CMP system (one simulation for 8 benchmarks in the following order: [gzip, vpr] [gcc, mcf] [crafty, parser] [eon, perlbmk]) and collect Instruction per Cycle (IPC) and level 3 cache miss rate for the simulations with different level 3 cache sizes (1MB, 2MB, 4MB, 8MB). Draw the following Excel figures to compare the differences and analyze the results.

Figure 3 and analysis: Total instruction per Cycle (IPC) for 4-core processor with different level 3 cache sizes. Total IPC is the sum of all cores IPCs)

Figure 4 and analysis: Level 3 cache miss rate for 4-core processor with different level 3 cache sizes.

report

Introduction and system architecture

Modification made in M5: New/modified files, configuration, parameters, classes, functions, etc. Where are the modified files? (Path and file name)

How to compile and run your program including how to setup the parameters?

Where are the results files?