In verilog, implement a Parallel$-$Input$-$Serial$-$Output $($PISO $8-$bit register. A PISO is a hardware structure that loads parallel data $($multiple bits$)$ on the input side and serializes it $($one bit at a time$)$ on the output side. The structure is a modification of a basic shift register with additional hardware to account for these functionalities.

Design an $8-$bit PISO register with input parallel$\_$in$[7$:$0]$ and output serial$\_$out $(1$ bit$)$ that will serialize the input in $8$ clock cycles. The first output bit is parallel$\_$in$[0]($LSB$-$first$)$ and then $1$ bit per cycle until parallel$\_$in$[7]($MSB$).$ The core of the shift register will be composed of the basic DFF described in class $($input d$,$ output q$,$ input clk$)$ and modified as needed to add the capability for an active$-$high synchronous reset $($input rst$).$ Additional gates may be needed in order to add the ability for the PISO module to load parallel data $($input load$)$ and shift data $($input shift$),$ both active$-$High inputs

I need the pen$-$and$-$paper$/$digital diagram for the PISO unit and a testbench for your testing purposes that shows clear timing diagram screenshots with at least ONE $8-$bit input passing through your PISO module.