Question: In verilog language: If you make a clock by executing this statement n a loop, that is it is executed over and over again #5

In verilog language: If you make a clock by executing this statement n a loop, that is it is executed over and over again #5 clk=~clk; Given that the testbench has this statement at the top `timescale 1ns/1ps What is the period of the clock (time from one positive edge to the next)

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