In which technique, does the CPU issue an I/O command, continues to execute subsequent instructions, and is interrupted by the I/O module when the latter has completed its work: a. I/O Registers b. Interrupts O c. 1/0 Channel O d. Programmed I/O Which technique frees up the CPU by transferring data directly between the I/O device and memory: O a. Programmed I/O O b. I/O Registers O c. I/O Channel O d. DMA Which of the following non-volatile memory is electrically erasable and programmable at the block level (multiple bytes at a time)? a. SDRAM O b. Flash C. EPROM O d. SRAM Which of the following ranks highest (smallest, most expensive, fastest access, most frequently accessed) in the memory hierarchy? a. CD-ROM O b. Cache L3 C. RAM d. Cache L1 A microprocessor has a 24 bit address bus and 16-bit data bus. What is the size of memory? a. 32 KB O b. 16 KB C. 32 MB d. 16 MB