Individual interrupt mask:

Select one or more:

a$.$

register in which addresses of devices reporting individual interrupts are stored

b$.$

a register whose bits are ORed $($alternative$)$ with the bits from the interrupt request register

c$.$

a register whose bits are ANDed $($conjunction$)$ with the bits from the interrupt request register

d$.$

a combinational circuit that calculates the number of the interrupt received