INFO: $[$VRFC $10-2263]$ Analyzing Verilog file $"$C:$/$Users$/$rha$31/$Downloads$/$Final Project$/$Final Project$/$Final Project.srcs$/$sources$\_1/$new$/$FSM$.$v$"$ into library xil$\_$defaultlib

INFO: $[$VRFC $10-311]$ analyzing module calculator$\_$fsm

WARNING: $[$VRFC $10-9336]$ redeclaration of ANSI port 'mode' is not allowed $[$C:$/$Users$/$rha$31/$Downloads$/$Final Project$/$Final Project$/$Final Project.srcs$/$sources$\_1/$new$/$FSM$.$v:$33]$

ERROR: $[$VRFC $10-2989]$ 'debounce$\_$cnt$\text{'}$ is not declared $[$C:$/$Users$/$rha$31/$Downloads$/$Final Project$/$Final Project$/$Final Project.srcs$/$sources$\_1/$new$/$FSM$.$v:$41]$

ERROR: $[$VRFC $10-2989]$ 'debounce$\_$cnt$\text{'}$ is not declared $[$C:$/$Users$/$rha$31/$Downloads$/$Final Project$/$Final Project$/$Final Project.srcs$/$sources$\_1/$new$/$FSM$.$v:$42]$

ERROR: $[$VRFC $10-2989]$ 'debounce$\_$cnt$\text{'}$ is not declared $[$C:$/$Users$/$rha$31/$Downloads$/$Final Project$/$Final Project$/$Final Project.srcs$/$sources$\_1/$new$/$FSM$.$v:$43]$

ERROR: $[$VRFC $10-2989]$ 'debounce$\_$cnt$\text{'}$ is not declared $[$C:$/$Users$/$rha$31/$Downloads$/$Final Project$/$Final Project$/$Final Project.srcs$/$sources$\_1/$new$/$FSM$.$v:$45]$

ERROR: $[$VRFC $10-8530]$ module 'calculator$\_$fsm$\text{'}$ is ignored due to previous errors $[$C:$/$Users$/$rha$31/$Downloads$/$Final Project$/$Final Project$/$Final Project.srcs$/$sources$\_1/$new$/$FSM$.$v:$21]$

module calculator$\_$fsm $($

input clk$,$

input btn$\_$mode, $//$ Single button for toggling modes

input $[1$:$0]$ btn$\_$sel, $//$ Operation selection input

output reg $[2$:$0]$ opcode,

output reg mode, $//0=$ Arithmetic, $1=$ Bitwise

output reg alu$\_$enable

$)$;

localparam MODE$\_1=1\text{'}$b$0$; $//$ Arithmetic operations

localparam MODE$\_2=1\text{'}$b$1$; $//$ Bitwise operations

reg mode $=$ MODE$\_1$; $//$ Initialize mode

reg btn$\_$mode$\_$sync; $//$ Synchronized button signal

reg btn$\_$mode$\_$debounced; $//$ Debounced button signal

$//$ Synchronize and debounce btn$\_$mode

always @$($posedge clk$)$ begin

btn$\_$mode$\_$sync $<=$ btn$\_$mode; $//$ Synchronize input to clock domain

if $($btn$\_$mode$\_$sync $!=$ btn$\_$mode$\_$debounced$)$ begin

debounce$\_$cnt $<=0$; $//$ Reset counter

end else if $($debounce$\_$cnt $<4\text{'}$d$15)$ begin

debounce$\_$cnt $<=$ debounce$\_$cnt $+1$; $//$ Increment counter

end

if $($debounce$\_$cnt $==4\text{'}$d$15)$ begin

btn$\_$mode$\_$debounced $<=$ btn$\_$mode$\_$sync; $//$ Update debounced signal

end

end

$//$ Toggle mode on falling edge of debounced button

always @$($posedge clk$)$ begin

if $($btn$\_$mode$\_$debounced && $!$btn$\_$mode$\_$sync$)$ begin

mode $<=$ ~mode; $//$ Toggle mode

end

end

$//$ Determine opcode based on mode and button inputs

always @$(*)$ begin

alu$\_$enable $=0$; $//$ Default disable ALU

case $($mode$)$

MODE$\_1$: begin

$//$ Arithmetic Mode

case $($btn$\_$sel$)$

$2\text{'}$b$00$: opcode $=3\text{'}$b$000$; $//$ Addition

$2\text{'}$b$01$: opcode $=3\text{'}$b$001$; $//$ Subtraction

$2\text{'}$b$10$: opcode $=3\text{'}$b$010$; $//$ Multiplication

$2\text{'}$b$11$: opcode $=3\text{'}$b$011$; $//$ Division

default: opcode $=3\text{'}$b$000$; $//$ Default to Addition

endcase

alu$\_$enable $=1$;

end

MODE$\_2$: begin

$//$ Bitwise Mode

case $($btn$\_$sel$)$

$2\text{'}$b$00$: opcode $=3\text{'}$b$100$; $//$ AND

$2\text{'}$b$01$: opcode $=3\text{'}$b$101$; $//$ OR

$2\text{'}$b$10$: opcode $=3\text{'}$b$110$; $//$ Shift Left

$2\text{'}$b$11$: opcode $=3\text{'}$b$111$; $//$ Shift Right

default: opcode $=3\text{'}$b$100$; $//$ Default to AND

endcase

alu$\_$enable $=1$;

end

default: begin

opcode $=3\text{'}$b$000$;

alu$\_$enable $=0$;

end

endcase

end

endmodule