Instruction:

Suppose that in some security I Block ciphers usually process 64 or 128-bit blocks at a time. To illustrate how their modes of operation work, we can use instead a pseudo-random permutation that operates on the 26 letters of the English alphabet: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 m A B C D E F G H I J K L M N O P Q R S T U V W X Y Z EK(m) P K X C Y W R S E J U D G O Z A T N M V F H L I B Q As the XOR operation is not defined on the set {A, . . . , Z}, we replace it here during encryption with modulo-26 addition (e.g., C D = F and Y C = A). (a) Encrypt the plaintext "TRIPOS" using: (i) electronic codebook mode; [2 marks] (ii) cipher-block chaining (using IV c0 = K); [4 marks] (iii) output feedback mode (using IV c0 = K). [4 marks] (Ab) Decrypt the ciphertext "BSMILVO" using cipher-block chaining.

In the context of multithreaded algorithms, define work and span, and state the work law and the span law. [3 marks] (b) Prove that the performance of a greedy scheduler is optimal to within a factor of 2. (Proving all intermediate theorems is not required if you state them correctly.) [4 marks] (c) Version A of a multithreaded algorithm takes 500 seconds on a uniprocessor machine and 50 seconds on a 32-processor machine. Version B takes the same time as A on a single processor but only 24 seconds on the 32-processor machine. (i) Define the parallelism of a computation and compute the parallelism of algorithms A and B. Which of the two has higher parallelism, and by how much? (Hint: use one of the greedy scheduler theorems to derive an approximation for one of the unknowns.) [6 marks] (ii) Estimate the running times of algorithms A and B on a 4-processor and on a 1024-processor machine, explaining how you obtain them. [3 marks] (iii) Sketch possible computation DAGs for algorithms A and B and use them to discuss the results obtained. As the number of processors in the host machine varies, is A or B faster? [4 marks] 2 CST.2014.3.3 2 Algorithms II (a) Consider van Emde Boas (v1EB) trees. (i) On its own page for legibility, draw the smallest vEB tree storing keys 0, 3, 6, 7. The correctness of the structure and the accuracy of all fields of all nodes are important. Once done, write each of the keys under the cluster in which it is logically stored. [8 marks] (ii) vEB trees store the minimum and maximum key of a subtree in the root node, but do not store the minimum key in any of the descendent clusters. Explain all the reasons why this provides a performance advantage compared with proto-vEB trees. [4 marks] (b) Consider proto-vEB trees. The following pseudocode attempts to implement a method to delete a key from a proto-vEB node. Give a clear explanation of the strategy that it uses.

(iv) Using a Karnaugh map, this time determine the required simplified Boolean expression for the output S in a minimum product-of-sums form. [10 marks] (b) Provide a circuit diagram which implements the following Boolean function using only NAND gates F = (A + D).(B + C + D).(A + B + C) that has the don't care states: A.B.C.D, A.B.C.D, A.B.C.D and A.B.C.D [4 marks] ( (a) Show how two NOR gates may be connected to form an RS latch. Describe its operation and give a table relating its inputs to its outputs. How could you use this circuit to eliminate the effect of contact bounce in a single pole double throw switch supplying an input to a digital logic circuit? [6 marks] (b) The state sequence for a particular 4-bit binary up-counter is as follows:

www.myfavouritesupermarket.com, and it needs to be usable by non-engineers. (a) For each of the following software project phases, suggest a design model or representation that would be a helpful aid in the design process. For each of these, sketch an example to show what this model looks like, based on some part of the above design brief.