is a design problem. Legibility and comprehensibility count. If we don't under

what you scribbled, you won't full credit even if the design that you have in

head is actually correct. $.$

Consider the shift register shown in Figure $1.$ Redesign it so that four bits can

be loaded, in parallel, when a load signal $L$ is set to one. Call these four values

the "seed" value. When $L$ is set to zero, it should shift.

We'll call this a Linear Feedback Shift Register $($LFSR$).$

What sequence of values will the LFSR cycle through if you load a seed of

$1000?$

What sequence of values will the LFSR cycle through if you load a seed of

$1111?$

What seguence of values will the LFSR cycle through if you load a seed of

$0101?$

$-$What seed value will NOT cause the LFSR to cycle through any values?