It is illegal to post this problem on Chegg or other online sites. Please refer to the ASM diagram below. It corresponds to the design in section $5\mathrm{.}8$ of Zybook. Remember that the outputs are asserted at the end of the state, in the transition to the next clock cycle $($one clock cycle delay$).$

Assume the machine has been in state S$\_$Q and for several clock cycles the input b$=0.$

During the first clock cycle b$=0,$ at the end of the cycle the value of T$=$ and N$=$

The second clock cycle b$=1,$ at the end of the cycle the value of T$=$ and N$=$

The third clock cycle b$=1,$ at the end of the cycle the value of T$=$ and N$=$

The fourth clock cycle b$=0,$ at the end of the cycle the value of T$=$ and N$=$

The fifth clock cycle b$=0,$ at the end of the cycle the value of T$=$ and N$=$