It is my term project.Could you please solve the question by explaining it in detail?

\begin{tabular}{|l|l} \begin{tabular}{l} Student Name: \\ Student ID: \end{tabular} & \begin{tabular}{l} EEE 303 Digital System Design \\ Term Project \end{tabular} \\ \hline & \begin{tabular}{l} Design a 3-digit lock circuit such that the lock \\ opens (=0) when 3-digit passcode pressed \\ sequentially and closed (=1) otherwise. The \\ passcode is the 018. The circuit has 10 inputs \\ each is 1-bit. Each input represents a decimal \\ number 0-9 as shown in the picture. Module \\ hasto start with: \\ module Sequencelock ( \\ input A0, A1, A2, A3, A4, A5, A6, A7, A8, A9, \\ output reg Lock \\ ); \end{tabular} \\ \hline \end{tabular} 1. Write the Verilog code in EDAplayground, Save it as "Public". Share the http link of the code here: 2. (40 points) Paste the design code inside this rectangle: 3. (40 points) Write a test bench in EDAplayground and paste the testbench code and the test output print results using \$monitor() inside this rectangle. First, enter 3 wrong digits with \#5 delay. If no key pressed or a pressed key released, 10 input bits become 0 (zero). 10 input bits has to become zero between each digit pressing. 4. (20 points) Synthesize the Verilog code using EDAplayground by selecting Yosys 0.9.0 Copy paste the diagram here