It is proposed to modify the MIPS multicycle processor design described in VHDL in order to allow pipeline instructions to be executed. The implementation of the pipeline architecture should include the detection and treatment of data conflicts through the automatic insertion of bubbles and the detection and treatment of control conflicts, allowing the deviation instructions to have the correct functioning. To simplify the project, the use of a data down payment is not mandatory. A VHDL simulator should be used to verify and validate the modifications made in the processor, allowing to test if the program soma_cte.asm, provided with the project, continues to function correctly. follow the codes below:

https://drive.google.com/file/d/1j-SWBEiYUhGJAeMxhUTzm9k5T6OQKkOg/view?usp=sharing

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