It is required to shown circuit using Verilog without simplification. The corresponding gate delays are also shown belovw Q.1. Gate Inverte 2-Input OR Delay l ns F2-Input AND ns a) Write expression implemented by the above circuit (without simplification) and then write the corresponding truth table circuit. [4 points] b) Write a Verilog module, called F_a, to model the gate level implementation of F for the above drawn circuit. I4 points]