Itanium 2 ALU self-bypass path is shown in the figure below. The propagation delays and contamination delays of the path are given in the table. Suppose the flip-flop registers have a setup time of 60 ps, hold time of -8 ps, and propagation delay of 80 ps, and contamination delay of 65 ps.
(a) Calculate the minimum cycle time Te at which the ALU self-bypass path will operate correctly.
(b) The earliest input to the late bypass multiplexer is the imm value coming from another flip-flop. Will this path experience any hold time violations?
(c) If the ALU path experiences 45 ps of skew from one cycle to the next between flip-flops in the various ALUS, what is the minimum cycle time of the system?
(d) How much clock skew can the system tolerate before hold time failure occur?