Keep in mind that branch instruction takes three clock cycles as shown in RISC$-$V architecture $($IMPORTANT$).$

Consider the following RISC$-$V mnemonic machine language program:

The RISC$-$V CPU is pipelined as explained in class : It has forwardings, delayed branches $($Delayed

branch means the compiler will place independent instruction or NOP if not found in the branch delay

slots no matter what the Branch outcome is$)$ and write$-$in$-$the$-$first$-$half, read$-$in$-$the$-$second$-$half register

usage. Assume also that there is a perfect memory, with no stalls.

The code above is written for the unpipelined RISC$-$V CPU since there are no independent instructions

after the LD and BNE instructions.

i$)$ Reorder the instructions to place independent instructions following the load instruction and in the

delayed branch slot. Note that the number of instructions after the reordering will be still six.

ii$)$ Show the execution of the program for two iterations for which you show AND EXPLAIN all the necessary

forwarding, register$-$reading$-$writing and resolved data hazard types as done in class.