LABORATORY INTERRUPT 1. 2. OBJECTIVE 1.1 Understanding the interrupt structure in the 8085 microprocessor INTRODUCTION The 8085 microprocessor has five (5) interrupt source input. They are TRAP, RST7.5, RST6.5, RST5.5 and INTR. TRAP is non maskable and the others are maskable. During reset, all the maskable interrupt are disable, so the microprocessor only responds to TRAP. For maskable interrupt to be effective, it must be enabled under program control. Only three (3) of this interrupt can be used using our 8085 development system: RST7.5, RST6.5 and RST5.5. The RST6.5 and RST5.5 are level sensitive while RST7.5 is rising edge sensitive. When the microprocessor is interrupted by the external device, it will respond to the interruption by completing their current instruction, saving the program counter of the next instruction to be executed onto the stack and then jumping to the following addresses based on the type of interrupt request. RST5.5 RST6.5 RST7.5 002CH 0034H 003CH These addresses are located in the ROM space. For the 8085 development board that is used in the laboratory, the interrupt address of RST5.5, RST6.5 and RST7.5 are redirect to the new address location at RAM space using JMP instruction. Therefore, the users can easily enter their code of JMP instruction to the interrupt service routine. The new addresses are listed below. RST5.5 RST6.5 RST7.5 3F2CH 3F34H 3F3CH You can examine the contents of memory location 002CH, 0034H and 003CH using D command (Display memory). Its contain three byte of instruction for each interrupt address. The code is C3 which is representing the opcode of JMP instruction and followed by another two byte of data represented the destination address. Two program steps are required to enable the RST7.5, RST6.5, RST5.5 interrupts: Clearing the interrupt masks using SIM instruction. Enabling all interrupt using El instruction The SIM instruction is used to implement the masking process of the 8085 interrupts RST7.5, RST6.5 and RST5.5. This instruction interprets the accumulator contents as follows: Microprocessor Laboratory Module SOD SOE R7.5 MSE M7.5 M6.5 M5.5 SOD - Serial Output Data: Bit D7 of Accumulator is latched into the SOD output line and made available to serial peripheral if bit D6 = 1 SOE - Serial Output Enable: If this bit = 1, it enables the serial output. To implement serial output, this bit needs to be enabled. X - Don't care R7.5 - Reset RST7.5: If this bit = 1, RST7.5 flip-flop is reset. This is an additional control to reset RST7.5. MSE - Mask Set Enable: If this bit is high, it enables the function of bits D2, D1 and DO. This is a master control over all the interrupt masking bits. If this bit is low, bits D2, D1 and DO do not have any effect on the masks. M7.5-D2 = 0, RST7.5 is enabled D2=1, RST7.5 is masked or disabled M6.5-D1 = 0, RST6.5 is enabled D1=1, RST6.5 is masked or disabled M5.5-D0=0, RST5.5 is enabled DO=1, RST5.5 is masked or disabled Note: SOD and SOE are irrelevant for interrupt setting. For example, the following instruction sequence enables RST6.5 and disables RST7.5 and RST5.5: MVI A, 00011001B SIM 3. EXERCISE Connect the circuit as shown in Figure 1 and write the following program. Test the program using the 8085 development system by pressing the pushbutton switch connected to RST6.5. 8255 Address Bus PAO LED Control Bus " LED Data Bus RST6.5 SW PUSHBUTTON Figure 1 Microprocessor ORG 2000H LXI SP, 3FF0H MVI A, 80H OUT 83H MVI A, 00011101B SIM ; Main program MAIN: MVIA, 11111110B OUT 80H CALL DELAY MVIA, 11111111B OUT 80H CALL DELAY JMP MAIN DELAY: LXI B, 65535 LOOP: DCX B MOV A, B ORA C JNZ LOOP RET ;Interrupt Service Routine RST6.5 ISR65: BLINK: PUSH PSW PUSH B MVI D, 10 MVI A, 11111110B OUT 81H CALL DELAY MVI A, 11111111B OUT 81H DCR D CALL DELAY JNZ BLINK POP B POP PSW EI RET ORG 3F34H JMP ISR65 END Laboratory Module Discuss your result. Connect another pushbutton switch to the RST5.5 pin. Modify your existing program to make the LED blink 20 times when the pushbutton switch (RST 5.5) is pressed