Question: Labs should be written for STM 3 2 Cube IDE. For the STM 3 2 F 4 4 6 xC / E ARM Cortex -
Labs should be written for STM Cube IDE. For the STMFxCE ARM Cortex Mb board. On programming language C Results should be provided like: step a and code below, step b and code below, for all parts and steps. And all explanations should be provided.
Template:
#include
#include
#include
#include stmfzeLib.h
#include stmfxxh
#define STEP
#define STEPb
#define STEP
test of interrupts with various priorityoccurrence conditions
int mainvoid
lcd.begin;
lcd.clear;
lcd.printchar INTERRUPT ;
global disable interrupts
init GPIO pins
Select interrupt source
unmask interrupt sources
select the active edge
Enable interrupt at NVIC level
#ifdef STEP
set priorities
#endif
global enable interrupts
#ifdef STEP
test INT handler & LEDs using software interrupt
#endif
while waiting for interrupt
Interrupt handlers
do not forget to modify startupstmfxxs file
do not forget to clear interrupt flag
void EXTIIRQHandlervoid
#ifndef STEPb
clear the INT flag here
#endif
your ISR code here
#ifdef STEPb
clear the INT flag here
#endif
void EXTIIRQHandlervoid
your code here
Part : Using interrupts
Note: Use the default HSI clock for the microcontroller. You are allowed to use the gpio functions available from the stmfzeLib library.
In violation of good programing practices, the ISR deliberately takes a long time to be able to verify the priority and preemption mechanisms.
STEP: Write a code that loops infinitely and:
a Blinks times LD with a blink period of ms on port PG when a falling edge occurs on port PB Keep the interrupt priority at its default value.
b Blinks times LD with a blink period of ms on port PG when a falling edge occurs on port PC Keep the interrupt priority at its default value
STEP: Add software interrupts to your code to test the interrupts without using the switches before entering the infinite loop
STEP: The interrupt flag can be cleared anywhere in the ISR. What happens for an new interrupt on EXTI which occurs while ISR is currently running:
a: if the flag is cleared at the very beginning of the ISR?
b: if the flag is cleared at its very end?
STEP: The interrupts are not simultaneous
a: Set the same priority level to both interrupts. Verify that an interrupt is memorized if it occurs while the other interrupt is being served ie no preemption How many events can be memorized for a given interrupt vector?
b: Same test but with a lower priority for EXTIIRQn. Verify preemtion of EXTIIRQHandler.
STEP: The interrupts are simultaneous ie connected to the same switch using the special cable provided
a: Test the behavior with the same priority for both interrupts. Which interrupt is served first and why?
b: Same test but with a lower priority for EXTIIRQn. Which interrupt is served first and why?
c: What happens if you press the switch twice during the execution of the ISR? Explain why.
d: Same test as before but pressing the switch times or more during the execution of the ISR? Explain.
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