Large$-$scale integrated $($LSI$)$ circuit chips are made in one department of an electronics

firm. These chips are incorporated into analog devices that are then encased in epoxy. The yield

is not particularly good for LSI manufacture, so the AQL specified by that department is $0\mathrm{.}15$

while the LTPD acceptable by the assembly department is $0\mathrm{.}40.$

$1)$ Develop a sampling plan that achieves a $5\%$ Type I error and a $10\%$ Type II error. The

corresponding sampling table is given below for your reference. $[10$ pts$]$

c LTPD$/$AQL n$*$AQL c LTPD$/$AQL n$*$AQL

$044\mathrm{.}8900\mathrm{.}05253\mathrm{.}5492\mathrm{.}613$

$110\mathrm{.}9460\mathrm{.}35563\mathrm{.}2063\mathrm{.}286$

$26\mathrm{.}5090\mathrm{.}81872\mathrm{.}9573\mathrm{.}981$

$34\mathrm{.}8901\mathrm{.}36682\mathrm{.}7684\mathrm{.}695$

$44\mathrm{.}0571\mathrm{.}97092\mathrm{.}6185\mathrm{.}426$

$2)$ Explain what the sampling plan means; that is$,$ how would you tell someone to do the test?

$[5$ pts$]$