LD F$0,0($R$1)$ DIVD F$2,$ F$0,$ F$1$ LD F$3,0($R$2)$ DIVD F$4,$ F$3,$ F$5$ ADDD F$0,$ F$2,$ F$6$ ADDD F$1,$ F$4,$ F$7$ SD F$1,0($R$2)$ ADDI R$1,$ R$1,$ #$8$ ADDI R$2,$ R$2,$ #$8$ SLTI R$3,$ R$1,$ #$800$ BGEZ R$3,$ foo

There are five stages: Fetch $($F$),$ Decode $($D$),$ Execution $($X$),$ Memory $($M$),$ and Write back $($W$).$ Each stage takes $1$ clock cycle except for the execution stage which takes a variable number of cycles depending on the functional unit used: $$ ALU Integer: $1$ clock cycle $$ FP$/$Integer multiplier: $4$ clock cycles, pipelined $$ FP adder: $2$ clock cycles, pipelined $$ FP$/$Integer divider: $5$ clock cycles, non$-$pipelined $$ All loads $($stores$)$ complete their memory access during Memory cycle. If there is any structural hazard, assume the earliest instruction gets priority and other instructions are stalled in Decode stage. In addition, a register read and a write in the same clock cycle forwards through the register file. a$)$ Show the timing of this instruction sequence for the above pipeline under which forwarding and bypassing hardware is implemented only for integer instructions. Assume that the branch is handled by predicting$-$it$-$as not taken and it is completed in two clock cycles. $(15$ points$)$ b$)$ Show the timing of this instruction sequence for the above pipeline under which forwarding and bypassing hardware is implemented for both integer and floatingpoint instructions. Assume that the branch is handled by predicting$-$it$-$as not taken and it is completed in two clock cycles. $(15$ points$)$ Note: All load and store instructions should be considered as the integer instructions.