Let's design an electrostatically actuated parallel$-$plate MEMS tunable capacitor. The capacitance and pull$-$in voltage are $0\mathrm{.}1$ pF and $10$ volts respectively. The initial gap between the two parallel plates is $\backslash (3\backslash$mu $\backslash$mathrm$\{$~m$\}\backslash ).$ The tunable capacitor consists of a bottom plate fixed on the substrate and a suspended top plate supported by four $($guided$)$ cantilever structures. The material of the two plates is doped polysilicon $(\backslash (\backslash$mathrm$\{$E$\}=120\backslash$mathrm$\{$GPa$\}\backslash ))$ with a thickness of $\backslash (1\mathrm{.}5\backslash$mu $\backslash$mathrm$\{$~m$\}\backslash ).$ The substrate is silicon coated with $\backslash (0\mathrm{.}5\backslash$mu $\backslash$mathrm$\{$~m$\}\backslash )$ thick silicon nitride for electrical isolation.

$(1)$ Develop a suitable fabrication process to make the tunable capacitor. Draw a clear cross$-$section diagram and also include a brief description for each of the major steps $($only deposition and etching while neglecting the lithography step$).$

$(2)$ Determine proper geometry and dimensions $(\backslash ($ x $\backslash )$ and $\backslash ($ y $\backslash ))$ to achieve the required capacitance and pull$-$in voltage.

$(3)$ Determine the required photolithography steps and use LEDIT or other layout software $($e$.$g$.,$ Cadence$)$ to design the mask layout for the fabrication of the tunable capacitor. Suitable alignment marks should be included in your mask layout.