Let's start with a memory system that is byte addressable and has 14-bit addresses. Now let's add a direct mapped cache that can hold 16 blocks (or has 16 lines) and each block is 4 bytes. The table shoun below details the contents of the cache at a particular point in time. if the valid bit is 1 there is a cache block loaded into the cache with Tag as detailed in the tag column. The columns B0-D3 then show the actual data in the cache block that s loaded in the cache. The ldx column is index for each of the positions in the cache Cantonts of a Cacha at a particular instanca af tima Valid BO 01 B1 B3 19 15 1B 36 23 24 51 08 93 15 3B OD 36 72 10 16 15 1B D3 Answer thc follawing questions for the cache as shawn: 1. How many bytes are in the main memory? 2. How many bytes can the cache hold? 3. How many blodks Is the main memory dlvided Into? 4. How many blode from the main memary want to be placed into slat in the cache? 5. Consider the following addresses that are each reading a single byte and detail whether they result in a hit er a miss in the cache. If the eddress results in a hit, then state the velue that gets sent to the processor. 0x0922, 0x2ACE, Ox14FC, 032, 0x1691 . Now go back to the original cache state ignore amy changes the above reads may have causedi and list 5 addresses, that are in 5 ditferent blocks. that all result in hits in the cache. 7, Now go back to the original cache state (ignore any changes the above reads may have causedi and list 5 addresses, that are in 5 different blocks, that all result in misses in the cache. and do not require data to be removed from the cache 8. Now po back to the original cache state (Enore any changes the above reads may have causedi, and list 5 addresses that are In 5 different blocks, that all result In misses In the cache and requlre data to be removed from the cache