: List the eight memory addresses (in hex) that will hit in set 2

Suppose we have a system with the following properties: The memory is byte addressable. Memory accesses are to 1-byte words (not to 4-byte words). Addresses are 13 bits wide. The cache is four-way set associative (E = 4), with a 4-byte block size (B = 4) and eight sets (S = 8). Consider the following cache state. All addresses, tags, and values are given in hexadecimal format The Index column contains the set index for each set offour lines. The Tag columns contain the tag value for each line. The y columns contain the valid bit for each line. The Bytes 0-3 columns contain the data for each line, numbered left-to-right starting with byte 0 on the left Suppose we have a system with the following properties: The memory is byte addressable. Memory accesses are to 1-byte words (not to 4-byte words). Addresses are 13 bits wide. The cache is four-way set associative (E = 4), with a 4-byte block size (B = 4) and eight sets (S = 8). Consider the following cache state. All addresses, tags, and values are given in hexadecimal format The Index column contains the set index for each set offour lines. The Tag columns contain the tag value for each line. The y columns contain the valid bit for each line. The Bytes 0-3 columns contain the data for each line, numbered left-to-right starting with byte 0 on the left