Load R$1,$ #$0$

Load R$2,$ A$($M$)$

Add R$2,$ R$1$

Load R$3,$ C$($O$)$

Sub R$2,$ R$3$

Load R$4,$ B$($N$)$

Multiply R$2,$ R$4$

Load D$($P$),$ R$2$

Consider the above segment of code. The code needs to be executed $75$ times for evaluating the vector arithmetic expression. The code contains four processor registers R$1,$ R$2,$ R$3$ and R$4$ and the starting memory location M$,$ N$,$ O$,$ and P for the respective arrays A$($M$),$ B$($N$),$ C$($O$),$ and D$($P$)$ respectively.

The Load or Store, Add or Sub and Multiply instructions require eight, five and twelve clock cycles respectively. The clock cycles mentioned work on both SISD and SIMD processors. Observe the processor cycles to be performed on SISD and SIMD by answering the following questions.

a$.$ Total number of processor clock cycles required to execute the above code $75$ times sequentially on SISD uniprocessor $($ignore the time delays$)$

b$.$ Total number of processor clock cycles required to execute the above code $75$ times using $75$ processing elements to execute the vector $107/20-202$ operations in eight synchronized vector instructions using $75-$component

vector data utilizing the same clock speed on SISD processor $($ignore the other broadcast and time delays$)$

c$.$ Compute the speedup performance gain between the SIMD and SISD computer processor.