Logic Designe / Digital Sign

Problem 1 (20 pts) Draw a schematic showing how the following Verilog module can be implemented using just registers, adders, and multiplexors. module small_datapath ( input clk, input [3:0] din, input en_W, input s_x, input enx, input [1:0] s_dout, input en_dout, output reg [3:0] dout reg [3:0] w; reg [3:0] x; always@ (posedge clk) if (en w) w