Question: Make supports macros, also called variables. Some common macros have standardized names: CC is the name of the compiler CFLAGS contains compiler flags, e .
Make supports macros, also called variables. Some common macros have standardized names: CC is the name of the compiler CFLAGS contains compiler flags, eg CFLAGS Wallstdc LDLIBS contains libraries to be included when linking, eg LDLIBS lm links the math library Special macros begin with a dollar sign and do not need to be surrounded by parentheses. See http:wwwcprogramming.comtutorialmakefilescontinued.html for more information. They can be used to avoid repeating target names and dependencies: $@ is the name of the target, often used after the o flag. $ stands for all dependencies, which is useful for linking rules. $ stands for the first dependency, which is useful after the c flag in compilation rules. Define the CC CFLAGS, and LDLIBS macros in your makefile with the appropriate values. Comment out the make rules that were added in section and replace them with new rules that use these macros and the listed special macros wherever possible. This final version must be the one that runs when make lab is called from the command line.
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