Match the term in the first column with its correct description in the second column. Temporal locality 1. The processor can't execute an instruction in the proper clock cycle because a needed resource is busy. Spatial locality 2. The address maps to a unique set in cache; (Block address) modulo (\# Sets in cache). Pipelining 3. A method of solving a control hazard by assuming a given outcome for the branch. - Direct mapped cache 4. Items near those accessed recently are likely to be accessed soon; like arrays data. N-way set associative cache 5. Shows the details of what is happening within the pipeline during each clock cycle. Control (Branch) hazard 6. Shows what is happening within the pipeline during ALL clock cycles. - Structural hazard 7. A cache structure in which a block can be placed in any location in the cache. Single clock cycle pipeline diagram 8. The address maps to a unique block in cache; (Block address) modulo (\# Blocks in cache). 9. Items accessed recently are likely to be accessed again soon; like instructions in loops. 10. A hazard arises from the dependence of one instruction on an earlier one that is still in the pipeline. 11. Next instruction is fetched before the previous one completes its execution (overlapping). 12. The processor is not clear about what the next instruction to fetch is