May I get the solution and answer for these questions? Thank you

ECB 4413 In a pipelined architecture, the individual stages of a datapath have the following latencies which are listed in TABLE Q1a 1. TABLE Q1a IF ID EX | MEM | WB 250ps 200ps150 ps300 ps 100 ps i Determine the clock cycle time in a pipelined and non- pipelined (single cycle) processor 2 marks ii. Determine the total latency of an LW instruction in a 2 marks How much time is needed by the pipelined processor to execute the following instructions? move $vo, szero add $vO, $vO, 1 s11 $vo, $v, 1 s11 $vo, sv, 1 2 marks How much time is needed by the single cycle processor 2 marks to execute the instructions listed in part (ili)