MINI PROJECT

Code the above design in verilog HDL and implement the same on the FPGA Kit allotted to you

Use Virtual input and Output IP Core for giving input $13,12,11,10$

CLK from the Kit.

Y$3$ Y$2$ Y$1$ Y$0$ need to be displayed on Chipscope IP Core.

$4-1$ Mux use dataflow

Decoder use behaviour modeling

Latch use behaviour modeling

Counter$-$ Use Xilinx IP Core.

Connect everything as miniproject.v and implement on the Kit