MIPS $5-$Stage Pipeline and Reorder buffer simulator

Consider the default setting given in the simulator. The following set of

instruction:

LD F$6$ F$0$ F$0$

LD F$2$ F$0$ F$0$

MULTD F$0$ F$2$ F$4$

SUBD F$8$ F$6$ F$2$

DIVD F$10$ F$0$ F$6$

ADDD F$6$ F$8$ F$2$

Deduce the following.

$($a$)$ Does the number of ROB entries affect the final clock cycle time in these two

cases?

i$)$ When an exception occurs. List the cycle time for ROB entries from $2-6.$

ii$)$ When there is no exception. List the cycle time for ROB entries from $2-6.$

$($b$)$ What is the impact of number of CDBs on total cycle time?

$($c$)$ Using the example set of instructions given, how can the scenario be changed

where only the use of multiple CDBs can help increase performance and ease

congestion?