MIPS Programming Question

Please, use question 1 to answer question 2

ONLY ANSWER QUESTION 2 PLEASE

There are 4 caches with the organization and block size as indicated below. All caches hold 128 words where each word is 4 bytes. Assuming a 32-bit address. A direct-mapped cache with block size of 16 words 2-way set-associative cache with block size of 8 words 4-way set-associative cache with block size of 4 words A fully associative cache with block size of 32 words. Here is a series of addresses in hexadecimal: 20(w), 3C(r), 10(r), 16(w), 20(r), 04(w), 28(r), 6(r), 10(w), 17(w) Assume a LRU replacement algorithm. For the four caches in problem 1, draw each cache as it would appear at the end of the series of references. Include the valid bit, dirty bit, and tag. Show the contents of the memory block using the byte address range such as M[20-23] for the word with address 22. There are 4 caches with the organization and block size as indicated below. All caches hold 128 words where each word is 4 bytes. Assuming a 32-bit address. A direct-mapped cache with block size of 16 words 2-way set-associative cache with block size of 8 words 4-way set-associative cache with block size of 4 words A fully associative cache with block size of 32 words. Here is a series of addresses in hexadecimal: 20(w), 3C(r), 10(r), 16(w), 20(r), 04(w), 28(r), 6(r), 10(w), 17(w) Assume a LRU replacement algorithm. For the four caches in problem 1, draw each cache as it would appear at the end of the series of references. Include the valid bit, dirty bit, and tag. Show the contents of the memory block using the byte address range such as M[20-23] for the word with address 22